1. Field of the Invention
The present invention relates generally to an integrated redundancy architecture, and more particularly to an integrated redundancy architecture for providing real-time built-in self-test (BIST) redundancy allocation to an embedded memory system.
2. Background of the Invention
Increasingly, system on chip (SOC) integrated circuit (IC) designs have gained momentum. As a result, the increasingly complex ICs often require large amounts of embedded memories to fulfill the SOC's functional requirements. In addition, it has become increasingly important to minimize the size of ICs. One way to accomplish this minimization, while still providing increased memory capacity is to use embedded dynamic random access memory (DRAM).
As circuit dimensions decrease, manufacturing the necessary structures often becomes more difficult. This results in the embedded memory cells becoming more prone to random defects and subsequent failure. When this trend is combined with the tendency to pack more memory bits on a chip, an effective way to repair the failing memory elements through the allocation of redundant memory becomes necessary.
Prior methods of redundancy allocation for embedded memories are based on the use of a row and column memory, whereby internally generated column and row addresses of defective columns and rows are stored. Usually the number of failing addresses that can be stored is equal to the number of redundant elements available for repair. Typically, as part of a built in self test (BIST), gross fails that exceed a certain threshold in a particular dimension are assigned to be stored in one of the redundancy memories, either a row or column, in a “must fix” pass. A second test pass identifies “sparse fails”, i.e., fails in a particular dimension that do not exceed the threshold used for determining gross fails, which are in turn stored in the remaining memory. This two-pass approach does not allow for optimum redundancy allocation as one cannot look at all the failing bits prior to assigning the redundancy.